Within integrated circuits it is important for the operation of circuit components that the supply voltage (Vdd) is accurately known and more importantly that the supply voltage is not allowed to fall below a predetermined threshold without some action been taken. Known solutions include providing circuits that compare the supply voltage directly with a reference voltage and provide as an output an indication when the two diverge by a predetermined factor. This indication can be used to reset other components within the integrated circuit chip or indeed to cause some other remedial action.
Problems with such known monitoring circuits include the fact that the monitoring circuit requires a constant monitoring of both the reference voltage (Vref) and the supply voltage (Vdd). This can result in the monitoring circuit having high power requirements. As a solution to this problem it is known to couple the supply voltage to a resistor divider string which provides a voltage to a capacitor, the stored capacitor providing an output which, although decaying according to the characteristics of the capacitor, is indicative of the supply voltage. By refreshing the capacitor at a periodic rate which is less than the decay value it is possible to reduce the power requirements of the circuit without reducing the monitoring performance. However such solutions still suffer in that the refresh is effected regardless of whether the refresh is required, therefore resulting in a turning on of the resistor divider network irrespective of whether it is required. Such indiscriminate coupling of the capacitor to the resistor string results in power being consumed.
There is therefore a need to provide an improved monitoring circuit and method that can provide an indication when the supply voltage falls below a predetermined threshold value yet does not have the same power requirements as the known solutions.